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Ordering number : ENA1352
Bi-CMOS IC
LV23015T
Overview
For Mini Component, receiver
1-chip Tuner IC Incorporating PLL
The LV23015T is a Single-chip tuner IC with built-in PLL for mini component, receiver.
Functions
* AM tuner * FM tuner * MPX stereo decoder * PLL frequency synthesizer
Specifications
Maximum Ratings at Ta = 25 C
Parameter Maximum supply voltage Maximum input voltage Symbol VCC max VIN1 max VIN2 max Maximum output voltage VO1 max VO2 max VO3 max Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VCC CE, CI, CL XIN DO XOUT, PD BO1, AOUT Ta70C *2 Conditions Ratings 7.0 7.0 *1 Vreg2+0.3 7.0 Vreg2+0.3 12.0 400 -20 to +70 -40 to +125 Unit V V V V V V mW C C
*1 Vreg2 : 21 pin output voltage (Reference voltage of PLL) Reference value (3.0V0.2V) *2 Specified board : 114.3mmx76.1mmx1.6mm, glass epoxy board.
* *
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Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
N0508 MS PC 20081020-S00019 No.A1352-1/17
LV23015T
Operating Condition at Ta = 25 C
Parameter Recommended supply voltage Operating supply voltage range Symbol VCC VCC op Conditions Ratings 5.0 4.0 to 6.0 Unit V V
PLL block Allowable Operating Range at Ta = -20C to +70C, VSS = 0V
Parameter Input high level voltage Input low level voltage Output voltage Symbol VIH VIL VO1 VO2 Operating frequency fIN1 fIN2 fIN3 fIN4 CE, CL, DI CE, CL, DI DO BO1, AOUT XIN ; VIN1 FMIN ; VIN2 AMIN (SNS = 1) ; VIN3 AMIN (SNS = 0) ; VIN4 10 2 0.5 Conditions Ratings min 0.7Vreg2 0 0 0 75 160 40 10 typ max 6.0 0.3Vreg2 6.0 10 Unit V V V V kHz MHz MHz MHz
Note : The XIN pin has extremely high input impedance, so that due care must be taken to prevent leakage.
Operating Characteristics at Ta = 25C, VCC = 5.0V, for the specified test circuit.
Parameter Symbol Conditions Ratings min typ max Unit
FM-FE characteristics : fc = 98MHz, fm = 1kHz, 22.5kHzdev. 3dB sensitivity -3dB LS 60dBV, 22.5kHzdev output reference, -3dB input Practical sensitivity QS S/N = Input at S/N = 30dB 8 5 (12) Reference value (15) Reference value FM oscillation voltage VOSC ST-BW No input, Pin 32 output, FET probe used 30 40 50 mVrms FM-EF stereo characteristics : fc = 98MHz, fm = 1kHz, 75kHzdev, L+R = 90%, Pilot = 10%, VIN = 60dBVEMF Stereo ON bandwidth ST-ON frequency bandwidth, 18pin (DO) output FM-IF monaural characteristics : fc = 10.7MHz, fm = 1kHz, 75kHzdev. Demodulation output Channel balance Signal to noise ratio AM suppression ratio VO CB S/N AMR 100dBV, 12pin output 100dBV, 12pin output 100dBV, 12pin output 70dBV input 12pin output reference, FM = no-mod, AM = 1kHz-30%mod, 12pin output Total harmonic distortion (monaural) 3dB sensitivity IF count sensitivity Mute attenuation 3dB LS IF-C3 Mute-Att 100dBV, 75kHzdev output reference, -3dB input SDC0 = 1, SDC1 = 0, 18pin (DO) output 100dBV, 12pin output 39 60 46 70 53 dBV dB 38 44 dBV THD 100dBV, 12pin output 0.6 1.5 % 750 -1.0 68 40 1000 0 74 50 1200 +1.0 mVrms dB dB dB (300) Reference value kHz dBV EMF dBV EMF
FM-IF stereo characteristics : fc = 10.7MHz, fm = 1kHz, Pilot = 10% Separation Total harmonic distortion (main) Total harmonic distortion (L only) Stereo ON sensitivity Capture range SEP THD-ST THD-L ST-ON CR 100dBV, L+R = 90%, L-mod, 12pin output/13pin output 100dBV, L+R = 90%, Main-mod, 12pin output 100dBV, L+R = 90%, L-mod, 12pin output 100dBV, L+R = 90%, Pin 18(DO) output Pilot = 10% modulated, Pin 18(DO) output 0.6 -0.4 1.0 0.6 2.0 2.0 6.5 +0.4 % % % kHz 28 38 dB
Continued on next page.
No.A1352-2/17
LV23015T
Continued from preceding page.
Parameter Symbol Conditions Ratings min typ max Unit
AM characteristics : fc = 1000kHz, fm = 1kHz, 30%mod Detection output 1 Detection output 2 Signal to noise ratio 1 Signal to noise ratio 2 Total harmonic distortion IF count sensitivity Mute attenuation Current drain FM tuner AM tuner PLL characteristics Built-in return resistor Built-in output resistor Hysteresis width Output high level voltage Output low level voltage Rf Rd VHIS VOH VOL2 VOL3 VOL4 Input high level current IIH1 IIH2 IIH3 Input low level current IIL1 IIL2 IIL3 Output off-leak current IOFF1 IOFF2 implemented. XIN XOUT CE, CL, DI PD ; IO = -1mA BO1 ; IO = 1mA BO1 ; IO = 5mA DO ; IO = 1mA AOUT ; IO = 1mA, AIN = 2.0V CE, CL, DI ; VI = 6.0V XIN ; VI = VDD AIN ; VI = 6.0V CE, CL, DI ; VI = 0V XIN ; VI = 0V AIN ; VI = 0V AOUT, BO1 ; VO = 10V DO ; VO = 6.0V 0.16 0.16 Vreg2-1.0 0.25 1.25 0.25 0.5 5.0 0.9 200 5.0 0.9 200 5.0 5.0 8 250 0.1Vreg2 M k V V V V V V A A nA A A nA A A ICCFM ICCAM No input at FM No input at AM 25 11 35 22 45 33 mA mA VO1 VO2 S/N1 S/N2 THD IF-C Mute-Att 23dBV, 12pin output 80dBV, 12pin output 23dBV, 12pin output 80dBV, 12pin output 80dBV, 12pin output 18pin (DO) output 80dBV, 12pin output 16 54 60 220 15 47 120 330 20 54 1.2 26 65 2.5 36 240 440 mVrms mVrms dB dB % dBV dB
Note : The reference value is calculated from more than one data and does not ensure conformance to the specifications. No data control by selection is
Package Dimensions
unit : mm (typ) 3253B
9.75 36 19
5.6
7.6
(0.5) (0.63)
1
0.18
18
0.15
0.08
(1.0)
SANYO : TSSOP36(275mil)
1.2max
0.5
No.A1352-3/17
DI
DI
(1) IN mode
(2) IN2 mode
0 1 0 P2 P3 P4 P5 P6 P7 P8 (1) P-CTR P9 P10 P11 P12 P13 P14 P15 SNS DVS (3) IF-CTR (13) Don't care CTE DNC R0 (2) R-CTR R1 R2 TEST1 TEST2 R3 P1
P0
Address
Address
(9) O-PORT (4) IFSW 0 (5) BDSW (14) STSW (15) SDC0 DOC0 (6) DO-C DOC2 (7) UNLOCK UL1 DZ0 DZ1 GT0 GT1 SDC1 DLC IFS TEST0 (12) TEST (8) DZ-C (3) IF-CTR (16) SDC1 (10) PD-C (11) IFS UL0 DOC1 SDC0 STSW BDSW1 IFSW
Composition of DI control data (serial data input)
10010100
00010100
BO1
LV23015T
No.A1352-4/17
LV23015T
Description of DI control Data
No. (1) Control/data Programmable divider data P0 to P15 DVS, SNS LSB varies depending on DVS and SNS. (* : don't care) DVS 1 0 0 SNS * 1 0 LSB P0 P0 P4 Set number of divisions (N) 272 to 65535 272 to 65535 4 to 4095 Actual number of divisions Twice the set value Set value Set value Description * Data to set the number of divisions of programmable divider Binary value using P15 as MSB. Related data
* LSB : P0 to P3 invalid when LSB is P4. * Selection of the signal input (FMIN, AMIN) to the programmable divider and switching of the input frequency. (* : don't care) DVS 1 0 0 (2) Reference divider data R0 to R3 SNS * 1 0 Input FMIN AMIN AMIN Operation frequency range 10 to 160MHz 2 to 40MHz 0.5 to 10MHz
* Data to select the reference frequency. R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 * PLL INHIBIT * Programmable divider and IF counter blocks stop, FMIN, AMIN, and IFIN inputs enter the pull-down state (GND), and the charge pump has high impedance. R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference frequency 25kHz 25kHz 25kHz 25kHz 12.5kHz 6.25kHz 3.125kHz 3.125kHz 5kHz 5kHz 5kHz 1kHz 3kHz 15kHz PLL INHIBIT+X'tal OSC STOP PLL INHIBIT
(3)
IF counter control data CTE GT0, GT1
* IF counter measurement start data CTE = 1 : Count start = 0 : Count reset * Determines the universal counter measurement time. GT1 0 0 1 1 GT0 0 1 0 1 Measurement time 4ms 8ms 16ms 32ms Wait time 3 to 4ms 3 to 4ms 3 to 4ms 3 to 4ms
IFS
(4)
MUTE IF count output SD time constant changeover control data IFSW
* Data to determine the output of the output port IFSW, controlling the MUTE function, IF count output (*1), and SD time constant changeover circuit (*2). "Data" = 0 : MUTE, IF count output, SD time constant changeover circuit-OFF (during normal reception) 1 : MUTE, IF count output, SD time constant changeover circuit-ON (during search of the desired station) *1 : IF counter buffer output entered in the IF counter circuit of the PLL logic block *2 : The rise time of AM-AGC voltage is shortened through rapid charge to the pin-25 external capacity when IFSW has been set to 1.
(5)
FM/AM BAND switch control data BDSW
* Data to determine the output of the output port BDSW, controlling switching of BAND. "Data" = 0 : AM 1 : FM
Continued on next page.
No.A1352-5/17
LV23015T
Continued from preceding page.
No. (6) Control/data DO pin control data DOC0 DOC1 DOC2 Description * Data to determine the output of the DO pin. DOC2 0 0 0 0 1 1 1 1 DOC1 0 0 1 1 0 0 1 1 DOC0 0 1 0 1 0 1 0 1 Open Low detection of unlock end-UC (See below) Open Open Low at SD ON Low at stereo Open DO pin state Related data UL0, UL1 CTE
* Open selected with power ON reset * IF counter measurement end check
DO pin (1) Count start (2) Count end (3) CE : HI
(1) DO pin open automatically when end-UC is set and the IF counter starts (CTE = 01). (2) DO pin becomes low, enabling check of the counter end when the IF counter measurement is over. (3) DO pin open with serial data input/output (CE pin : Hi) Note)DO pin open regardless of the DO pin control data (DOC0 to 2) during data input period (IN1 and IN2 modes CE-Hi period). The DO pin state allows output of the content of internal DO serial data in synchronization with CL regardless of the DO pin control data (DOC0 to 2) during data input period (OUT mode CE : Hi period). (7) Unlock detection data UL0, UL1 * Data to select the phase error (E) detection width to determine if PLL is locked. Unlock is determined when the phase error exceeding the detection width occurs. (* : don't care) UL1 0 0 1 UL0 0 1 * E Detection width Stop 0 6.67s Detection output Open E output directly E extended by 1 to 2ms DOC0 DOC1 DOC2
* unlock : DO pin becomes Low and the serial data output becomes UL = 0. (8) Phase comparator control data DZ0, DZ1 * Data to control the dead band of phase comparator. DZ1 0 0 1 1 (9) Output port data BO1 (10) Charge pump control data DLC DZ0 0 1 0 1 Deadband mode DZA DZB DZC DZD
Dead band : DZA < DZB < DZC < DZD * Data to determine the output of output ports BO1 "Data" = 0 : OPEN 1 : Low * Data for forced control of the charge pump output DLC 0 1 Charge pump output Normal operation Forced Low
When the VCO control voltage (Vtune) develops dead lock because of stop of oscillation of VCO at 0V, set the charge pump output to LOW and Vtune to VCC to escape the dead lock. (Dead lock clear circuit) (11) (12) IFS LSI test data TEST0 to 2 * Normally, set data = 1. Setting the data = 0 causes worsening of the input sensitivity, resulting in decrease of the sensitivity by about 10 to 30mVrms. * LSI test data TEST0 TEST1 TEST2 All set to 0 for power ON reset (13) DNC * Set data = 0. All to be set to "0"
Continued on next page. No.A1352-6/17
LV23015T
Continued from preceding page.
No. (14) Control block data Forced monaural control data STSW (15) (16) SD sensitivity adjustment data SDC0 SDC1 function "Data" = 0 : MONO 1 : STEREO * Data to determine the output of output ports SDC0 and SDC1, setting the SD sensitivity "Data" = SDC0 : 0, SDC1 : 0 SD sensitivity = 50dBV (Typ) SDC0 : 0, SDC1 : 1 SD sensitivity = 53dBV (Typ) SDC0 : 1, SDC1 : 0 SD sensitivity = 59dBV (Typ) SDC0 : 1, SDC1 : 1 SD sensitivity = 64dBV (Typ) Description * Data to determine the output of the output port STSW, controlling the forced monaural stereo Related data
Composition of the DO control data (serial data output) (1) OUT mode
Address DI 01010100
SDIND
STIND
C19
C18
C17
C16
C15
C14
C13
C12
C11
UL
C9
C8
C7
C6
C5
C4
C3
C2
C1
Description of DO output data
No. (1) Control/data Stereo indicator SD indicator Control data STIND, SDIND (2) PLL unlock data UL (3) IF counter Binary counter C19 to C0 * Data latching the content of the unlock detection circuit UL0 : At unlock 1 : At lock or detection stop mode * Data latching the content of IF counter (20 bit binary counter) C19MSB of binary counter C0 LSB of binary counter CTE GT0 GT1 UL0 UL1 Description * Data latching stereo indicator and SI indicator states. Latch made at a time of the data output mode (OUT mode). STINDStereo indicator state SDINDSD indicator state 0 : ST ON, 1 : ST OFF 0 : SD ON, 1 : SD OFF Related data
(1) IN-PORT
(3) IF-CTR
C0
DO
C10
0
No.A1352-7/17
LV23015T
Serial data input (IN1/IN2) tSU, tHD, tEL, tES, tEH 0.75s tLC < 0.75s
(1) CL : normal Hi tEL CE CL tSU DI Internal data B0 tHD B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC tES tEL
(2) CL : normal Low tEL CE CL tSU DI Internal data B0 tHD B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC tES tEL
Serial data output (OUT) tSU, tHD, tEL, tES, tEH 0.75s tDC, tDH < 0.35s
(1) CL : normal Hi CE CL tSU DI DO B0 tHD B1 B2 B3 A0 A1 A2 A3 tDH I2 tDH I1 UL C3 C2 C1 tDH C0 tEL tES tEL
(2) CL : normal Low CE CL tSU DI DO B0 tHD B1 B2 B3 A0 A1 A2
tEL
tES
tEL
A3 tDH I2 tDH I1 UL C3 C2 C1 tDH C0
Note : The DO pin is an Nch open drain pin, so that the data change time (tDC, tDH) changes depending on the pull-up resistance and substrate capacity.
No.A1352-8/17
LV23015T
Serial data timing
CE tCH CL VIH DI VIL tSU DO tHD VIL VI VIL VIH tCL VIL
VIH
VIL
VIH tEL tES
VIL
VIH tEH
tDC
tDC
tDH
tLC Internal data latch Old New
<< CL stopped at "L" level >>
CE tCH CL VIH VIL VIH DI VIL DO tSU tHD VIL VIH tCL VIH
VIH
VIL
VIL tEL tES
VIH tEH
tDC
tDH
tLC Internal data latch Old New
<< CL stopped at "H" level >>
Parameter Data setup time Data hold time Clock L level time Clock H level time CE wait time CE setup time CE hold time Data latch change time Data output time
Symbol tSU tHD tCL tCH tEL tES tEH tLC tDC tDH
Pin DI, CL DI, CL CL CL CE, CL CE, CL CE, CL
Conditions
Min 0.75 0.75 0.75 0.75 0.75 0.75 0.75
Typ
Max
Unit s s s s s s s s s
0.75 DO, CL DO, CE Varies depending on the pull-up resistance and substrate capacity 0.35
No.A1352-9/17
Block Diagram
+B
BPF + + + 32 LPF FM OSC SD OSC BUFFER AM AGC FM S-METER FF FF AM DET AM MIX AM IF VCC1 5 6 7 8 9 10 IF BUFFER 11 12 L-OUT + 450kHz 10.7MHz + +B + + 13 R-OUT -COM 14 FM IF FM DET PILOT DET PHASE MUTE COMP DATA SHIFT REGISTOR LATCH DECODER UNIVERSAL COUNTER CCB I/F 15 16 ST TRIG ST SW FF VCO PROGRAMABLE SWALLOW DIVIDER COUNTER AM OSC 31 30 29 28 27 26 25 24 23 22 21
X'tal 75kHz
36
35
34
33
20 REG2 POWER ON RESET
19
GND2
VCC2
FM RF
PHASE DETECTOR CHARGE PUMP
REFERENCE DIVIDER UNLOCK DETECTOR
LV23015T
FM MIX
AM RF
REG
GND1
1
2
3
4
17
18 REG2
AM ANT
+
VCC
No.A1352-10/17
Vt = 8V 0.047F 33k SVC347 3.3k 0.047F 1000pF 4.7F 51k 1.2k
1F 22F 910pF 3300pF
390 pF 16pF
Test Circuit
0.047F
33k 10 1000pF + + 0.1F 20k +18k 10pF
CFV-206 SVC201 FM RF SA-149
33k
SVC201
SA-181 SA-151 FM OSC 33pF
FM RF IN 51
10pF
+ 100F 0.1F
10pF 100k 75kHz
100k
8pF
AM RF IN 1 0.047F VCC1 6 1F 3.3k +
1000pF
SW9 29 BO1 A-OUT A-IN FM-S METER AM AGC AM FM DET OUT DET OUT 28 27 26 25 24 23 22 MPX IN
SW8
SW7
+ 4.7F
36 FM OSC AM OSC
35
34
33
32
31
30
21 VDD
SW5 20 X-OUT
SW4 19 X-IN
FM RF IN
GND2
FM FM VCC2 BYPASS RF OUT
LV23015T
REG 2
FM MIX 3
GND1 /VSS 4
AM MIX 5
AM IF IN 7
FM IF IN 8
FM P-DET P-COMP DET 9 10 11
L-OUT R-OUT 12 13 L-OUT
2.2k
SD IND 14 R-OUT
2.2k
CE 15
DI 16
CL 17
DO 18 SW2 -COM SW3 10k
AM ANT
SA-164
51
39mH
4700pF
4700pF
600BNAS-10963Z
SFELA10M7GA00-B0
SFULA450KU2B-B0
0.047F
+
10F
+ 0.47F 10k + 1F
0.047F FM IF IN 51
+ 100F
+B = 9V 300 0.047F VCC = 5.0V
No.A1352-11/17
LV23015T
LV23014T Pin description and pin voltage (VCC = 5.0V, +B = 9.0V)
No. 1 Pin name AM RF input Pin description Connect the AM ANT coil between this pin and pin 2 (Vreg1). No input voltage (V) AM Vreg1 FM Vreg1 Internal equivqlent circuit
2 1
2
REG1
Reference voltage of AM/FM, IF/MPX block
2.2
2.2
2
3
FM MIX output
Rout = 270
(2/3) VCC (2/3) VCC -0.5 -0.7
3 Rout
4 5
GND1 AM MIX output
GND of AM/FM, IF/MPX block Connect the AM MIX coil between this pin and pin 6 (VCC voltage).
0 VCC
0 VCC
5
6
6 7
VCC1 AM IF input
VCC of AM/FM, IF/MPX block Rin = 2k
5.0 Vreg1
5.0 Vreg1
7 Rin 2
8 FM IF input Rin = 330 Vreg1 Vreg1
8 Rin 2
9 Pilot filter R = 10k VCC-1 VCC-1
9
R
Continued on next page.
No.A1352-12/17
LV23015T
Continued from preceding page.
No. 10 Pin name Phase comparator filter R = 10k Pin description No input voltage (V) AM VCC-1 FM VCC-1 Internal equivqlent circuit
10
R
11
FM DET
Connect the FM DET coil between this pin and pin 6 (VCC voltage). Recommended detection coil : 600BNAS-10963Z by TOKO.
VCC
VCC
11
12 13 L output R output Resistance 2.2k for output level adjustments is connected between pin 12/13 and +B (+9V). R = 600 6.0 6.0 6.0 6.0
12
(
R
13
)
14
SD IND
SD indicator Active low output. R = 30k
Vreg2
Vreg2
21 R
14
15
CE
Chip enable port At changeover from "L" to "H" address latching. At changeover from "H" to "L" data latching.
15
16
DI
Serial data input port Sets data in synchronization with rise of data clock.
16
17
CL
Data clock input port
17
18
DO
Data output port Outputs various data in synchronization with fall of data clock in the out mode.
18
Continued on next page.
No.A1352-13/17
LV23015T
Continued from preceding page.
No. 19 20 XIN XOUT Pin name Pin description Clock for internal reference Connect 75kHz crystal oscillator. No input voltage (V) AM FM Internal equivqlent circuit
19 20
21
VREG2
Reference voltage of PLL block
3.0
3.0
21
22
MPX input
Rin = 20k
Vreg1
Vreg1
2 Rin 22
23
FM detection output
The separation can be adjusted with an external capacitor connected between this pin and GND. Rout = 3.3k
0.8
Vreg1
Rout 23
24
AM detection output
AM low frequency characteristic can be adjusted with an external capacitor connected between this pin and GND. Rout = 5.0k
2.0
0
Rout 24
25
AM AGC output
R = 13.8k
0.8
0
25 R
26
FM S-meter output and FM SD adjust
The FMSD sencitivity can be adjusted with an external resistor connected between this pin and GND. R = 14.0k
0
0.8
26 R
27 28
AIN AOUT
Nch MOS transistor for PLL active low pass filter.
1k
27
28
Continued on next page.
No.A1352-14/17
LV23015T
Continued from preceding page.
No. 29 Pin name BO1 Pin description General purpose output port No input voltage (V) AM FM Internal equivqlent circuit
29
30
AM OSC
AM OSC circuit with ALC AM OSC coil used between pins 31 and 6 (VCC voltage).
VCC
VCC
30
6
31
FM OSC
R = 10k C1 = 10pF C2 = 20pF
VCC
4.95
32 R 31 C1 C2
32 33 34 35
VCC2 FM RF output FM bypass FM RF input
VCC of FM FE block FM RF coil used between pins 33 and 32 (VCC voltage). The capacity of 1000pF is connected between pins 34 and 35 (GND). Rin = 1.5k
5.0 VCC 0 0
5.0 VCC 1.6
33
32 34
0.9
36 Rin
35
GND2
GND of FM FE block
0
0
No.A1352-15/17
Vt = 9V 0.047F 33k 3.3k
0.047F
Application Circuit
33k
1000pF
390pF 15pF
SVC201
4.7F 1.2k 10F 0.1F 22 21 22k + 18k 4.7F 23 + 10pF
SA-149
100k
8pF SVC201 1000pF
FM IN
9pF
GFWB7
1000pF
10pF X'tal 75kHz 20 19 X-IN
1F
+ 25 24
0.01F
22F
SA-181 SA-151 33pF 820pF
0.047F
10k 33 FM OSC AM OSC BO1 A-OUT A-IN FM-S METER 32 31 30 29 28 27 26 AM IF IN 7 P-DET 9 0.47F 1F + + 3.3k FM IF IN 8 FM P-COMP DET L-OUT 10 11 12 13 R-OUT 14 L-OUT R-OUT SD IND 15
AM ANT
SVC347 SFU450A SA-164 2.2k 4700pF 2.2k 47pF
SD + 1F 10k
36
35
34
FM RF IN
GND2
FM VCC2 FM BYPASS RF OUT
AM AM FM MPX REG2 X-OUT AGC DET OUT DET OUT SIGNAL IN
LV23015T
AM RF IN 1
FM AM REG MIX OUT GND1 MIX OUT VCC1 2 3 4 5 6
CE DI CL 16 17
DO 18 10k -COM
4700pF
SFELA10M 7FA00-B0
+ + 100F 0.047F
0.047F
10F
600BNAS -10963Z
+B = 9.0V
VCC = 5.0V
No.A1352-16/17
LV23015T
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of November, 2008. Specifications and information herein are subject to change without notice. PS No.A1352-17/17

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